Free the BVH tree immediately along with the mesh, otherwise we might access
invalid mesh data.
Differential Revision: https://developer.blender.org/D4201
Not only were those often making doublons with already existing
BLI_math's stuff, but they were also used to hide implicit type
conversions...
As usual this adds some more exotic inlined vector functions (one of
the rare cases where I really miss C++ and its templates... ;) ).
Avoids nasty code all over where such math is required, and
compilers can easily deal with such situation.
Don't prefer questionable micro-optimization which comes with
a cost of nasty actual logic code.
There is no point having operations that iterate over the whole
bit array as macros, so convert BLI_BITMAP_SET_ALL to a function.
Also, add more utilities for copying and manipulating masks.
Reviewers: brecht, campbellbarton
Differential Revision: https://developer.blender.org/D4101
The new data structure uses open addressing instead of chaining to resolve collisions in the hash table.
This new structure was never slower than the old implementation in my tests. Code that first inserts all edges and then iterates through all edges (e.g. to remove duplicates) benefits the most, because the `EdgeHashIterator` becomes a simple for loop over a continuous array.
Reviewer: campbellbarton
Differential Revision: D4050
This makes the `#include <Windows.h>` use more localised and out of the
`image.c` file.
Reviewers: LazyDodo
Reviewed by: LazyDodo
Differential revision: https://developer.blender.org/D4049
To make the pool more usable for running multiple stages of tasks,
fix local queue handling in BLI_task_pool_work_and_wait.
Specifically, after the wait loop the local queue should be empty,
or the wait part of the function contract isn't fulfilled. Instead,
check and run any tasks in queue before the wait loop.
Also, add a new function that resets the suspended state of the pool.
The idea is to make main thread and job threads to be scheduled
on CPU dies which has direct access to memory (those are NUMA
nodes 0 and 2).
We also do this for new EPYC CPUs since their NUMA nodes 1 and 3
do have access but only to a higher range DDR slots. By preferring
nodes 0 and 2 on EPYC we make it so users with partially filled
DDR slots has fast memory access.
One thing which is not really solved yet is localization of
memory allocation: we do not guarantee that memory is allocated
on the closest to the NUMA node DDR slot and hope that memory
manager of OS is acting in favor of us.
